1. Field of the Invention
The present invention relates to a vacuum prober and vacuum probe method which test the electrical characteristics of an object to be tested in a vacuum environment.
2. Description of the Related Art
In a process of manufacturing a semiconductor device, a probe system is used to test the electrical characteristics of a device formed on a wafer in a vacuum environment.
Patent reference 1 (Jpn. Pat. Appln. KOKAI Publication No. 2000-260839) discloses a low-temperature testing device in which a so-called prober chamber is entirely used as a vacuum vessel. In this low-temperature testing device, the entire prober chamber must be evacuated to produce a vacuum environment. Accordingly, evacuation takes time. Patent reference 1 discloses nothing concerning shortening of the evacuation time. Patent reference 1 does not disclose an alignment technique for a sample and probe needles, either.
Patent reference 2 (Jpn. Pat. Appln. KOKAI Publication No. 7-37945) discloses the following prober having an alignment mechanism. A container for accommodating a table and a multilevel interconnection substrate having a pump, the container is formed to be dividable into a cover portion and base portion. An optical unit integrally having upper and lower cameras is introduced between the cover and base portions, to image probes and electrode pads of an object to be tested. This prober, however, is not a vacuum prober that performs testing in a vacuum environment as in the present invention. This prober employs the optical unit which integrally has the upper and lower cameras. Such an optical unit has a complicated structure, and the focusing mechanisms of the two cameras require a specific contrivance.
Patent reference 3 (Jpn. Pat. Appln. KOKAI Publication No. 2004-128202) describes a prober in which a vacuum chamber is arranged in a prober chamber. A table is arranged in the vacuum chamber to test the electrical characteristics of a device in the vacuum chamber.
In this prober, however, the table cannot be moved in the X, Y, and Z directions in the vacuum chamber. To test the electrical characteristics of a plurality of devices formed on one wafer, steps of formation of an atmospheric environment→formation of a vacuum environment→testing must be repeated for the respective devices, leading to low throughput.